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ia8044/ia8344 data sheet sdlc communications contr oller march 30, 2010 ia211010112 - 0 4 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 1 of 65 1 - 888 - 824 - 4184 ia8044/ia8344 sdlc communications controller data sheet ? ?
ia8044/ia8344 data sheet sdlc communications contr oller march 30, 2010 ia211010112 - 0 4 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 2 of 65 1 - 888 - 824 - 4184 copyright 2010 by innovasic semiconductor, inc. published by innovasic semiconductor, inc. 3737 princeton drive ne, suite 130, albuquerque, nm 87107 intel is a registered trademark of intel corporation . miles? is a trademark of innovasic semiconductor, inc. ?
ia8044/ia8344 data sheet sdlc communicat ions controller march 30, 2010 ia211010112 - 0 4 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 3 of 65 1 - 888 - 824 - 4184 table of contents list of figures ................................ ................................ ................................ ................................ .. 6 list of tables ................................ ................................ ................................ ................................ ... 7 1. introduction ................................ ................................ ................................ ............................. 9 1.1 features ................................ ................................ ................................ ......................... 9 1.2 variants ................................ ................................ ................................ ....................... 10 2. packaging, pin descriptions, and physical dimensions ................................ ....................... 10 2.1 pdip package ................................ ................................ ................................ .............. 11 2.2 pdip physical dimension s ................................ ................................ .......................... 13 2.3 plcc package ................................ ................................ ................................ ............. 14 2.4 plcc physical dimensions ................................ ................................ ........................ 16 3. maxi mum ratings and dc characteristics ................................ ................................ .......... 17 4. functional description ................................ ................................ ................................ .......... 17 4.1 functional block diagram ................................ ................................ .......................... 17 4.2 input/output characteristics ................................ ................................ ....................... 19 4.3 memory organization ................................ ................................ ................................ . 20 4.3.1 program memory ................................ ................................ ............................ 20 4.3.2 external data memory ................................ ................................ ................... 20 4.3.3 internal data memory ................................ ................................ ..................... 20 4.3.4 bit addressable memory ................................ ................................ ................ 22 4.4 special function registers ................................ ................................ .......................... 23 4.5 ports ................................ ................................ ................................ ............................. 24 4.6 port registers ................................ ................................ ................................ .............. 24 4.6.1 port 0 (p0) ................................ ................................ ................................ ....... 24 4.6.2 port 1 (p1) ................................ ................................ ................................ ....... 25 4.6.3 port 2 (p2) ................................ ................................ ................................ ....... 25 4.6.4 port 3 (p3) ................................ ................................ ................................ ....... 25 4.7 timers/counters ................................ ................................ ................................ .......... 26 4.7.1 timers 0 and 1 ................................ ................................ ................................ 26 4.7.2 mode 0 ................................ ................................ ................................ ............ 26 4.7.3 mode 1 ................................ ................................ ................................ ............ 27 4. 7.4 mode 2 ................................ ................................ ................................ ............ 27 4.7.5 mode 3 ................................ ................................ ................................ ............ 27 4.7.6 timer mode (tmod) ................................ ................................ ..................... 27 4.7.7 t imer control (tcon) ................................ ................................ ................... 28 4.7.8 timer 0 high byte (th0) ................................ ................................ ............... 29 4.7.9 timer 0 low byte (tl0) ................................ ................................ ................ 29 4.7.10 timer 1 high byte (th1) ................................ ................................ ............... 29 4.7.11 timer 1 low byte (tl1) ................................ ................................ ................ 29 4.7.12 timer/counter configuration ................................ ................................ ......... 30 4.8 general cpu registers ................................ ................................ ................................ 32 ?
ia8044/ia8344 data sheet sdlc communicat ions controller march 30, 2010 ia211010112 - 0 4 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 4 of 65 1 - 888 - 824 - 4184 4.8.1 accumulator (acc) ................................ ................................ ........................ 32 4.8.2 b register (b) ................................ ................................ ................................ . 32 4.8.3 program status word (psw) ................................ ................................ .......... 32 4.8.4 stack pointer (sp) ................................ ................................ ........................... 33 4.8.5 data pointer (dptr) ................................ ................................ ...................... 33 4.9 interrupts ................................ ................................ ................................ ..................... 34 4.9.1 external interrupts ................................ ................................ .......................... 34 4.9.2 timer 0 and timer 1 interrupts ................................ ................................ ...... 34 4.9.3 serial interface unit interrupt ................................ ................................ ......... 34 4.9.4 interrupt pri ority level structure ................................ ................................ ... 34 4.9.5 interrupt handling ................................ ................................ .......................... 35 4.9.6 interrupt priority register (ip) ................................ ................................ ........ 35 4.9.7 interrupt enable register (ie) ................................ ................................ ........ 36 4.10 siu serial interface unit ................................ ................................ .......................... 36 4.10.1 siu special func tion registers ................................ ................................ ...... 37 4.10.2 serial mode register (smd) ................................ ................................ .......... 37 4.10.3 status/command register (sts) ................................ ................................ .... 38 4.10.4 send/receive count register (nsnr) ................................ ........................... 39 4.10.5 station address register (stad) ................................ ................................ .. 40 4.10.6 tra nsmit buffer start address register (tbs) ................................ .............. 40 4.10.7 transmit buffer length register (tbl) ................................ ......................... 40 4.10.8 transmit control byte regist er (tcb) ................................ .......................... 40 4.10.9 receive buffer start address register (rbs) ................................ ................ 41 4.10.10 receive buffer length register (rbl) ................................ .......................... 41 4.10.11 receive field length register (rfl) ................................ ............................. 41 4.10.12 receive control byte register (rcb) ................................ ............................ 41 4.10.13 dma count register (dma cnt) ................................ ................................ 42 4.10.14 dma count register (fifo) ................................ ................................ .......... 42 4.10.15 siu state counter (siust) ................................ ................................ ............ 42 4.11 data clocking options ................................ ................................ ................................ 43 4.12 operational modes ................................ ................................ ................................ ...... 43 4.13 f rame format options ................................ ................................ ................................ 44 4.14 hdlc restrictions ................................ ................................ ................................ ...... 46 4.15 siu details ................................ ................................ ................................ .................. 46 4.15.1 bip ................................ ................................ ................................ .................. 46 4.15.2 byp ................................ ................................ ................................ ................. 48 4.16 diagnostics ................................ ................................ ................................ .................. 48 5. ac speci fications ................................ ................................ ................................ ................. 50 5.1 memory access waveforms ................................ ................................ ....................... 51 5.2 serial i/o waveforms ................................ ................................ ................................ .. 55 ?
ia8044/ia8344 data sheet sdlc communicat ions controller march 30, 2010 ia211010112 - 0 4 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 5 of 65 1 - 888 - 824 - 4184 6. reset ................................ ................................ ................................ ................................ ..... 56 7. instruction set ................................ ................................ ................................ ....................... 57 8. innovasic/intel part number cross - reference tables ................................ ......................... 61 9. errata ................................ ................................ ................................ ................................ ..... 62 9.1 summary ................................ ................................ ................................ ..................... 62 9.2 detail ................................ ................................ ................................ ........................... 62 10. revision history ................................ ................................ ................................ ................... 64 11. for additional information ................................ ................................ ................................ ... 65 ?
ia8044/ia8344 data sheet sdlc communicat ions controller march 30, 2010 ia211010112 - 0 4 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 6 of 65 1 - 888 - 824 - 4184 list of figures figure 1. ia8044 and ia8344 40 - lead pdip package diagram ................................ .................. 11 figure 2. pdip physical package dimensions ................................ ................................ ............. 13 figure 3. ia8044 and ia8344 44 - pin plcc package diagram ................................ ................... 14 figure 4. plcc physical package dimensions ................................ ................................ ............ 16 figure 5. functional block diagram ................................ ................................ ............................ 18 figure 6. internal data memory addresses 00h to ffh ................................ ............................... 21 figure 7. timer 0 mode 0 ................................ ................................ ................................ ............. 30 figure 8. timer 0 mode 1 ................................ ................................ ................................ ............. 30 figure 9. timer 0 mode 2 ................................ ................................ ................................ ............. 31 figure 10. time r 0 mode 3 ................................ ................................ ................................ ........... 31 figure 11. bit and byte processors ................................ ................................ ............................... 47 figure 12. diagnostic signal routing ................................ ................................ ........................... 49 figure 13. program memory read cycle ................................ ................................ ..................... 52 figure 14. data memory read cycle ................................ ................................ ........................... 53 figure 15. data me mory write cycle ................................ ................................ .......................... 54 figure 16. synchronous data transmission ................................ ................................ ................. 55 figure 17. synchronous data reception ................................ ................................ ...................... 55 ?
ia8044/ia8344 data sheet sdlc communicat ions controller march 30, 2010 ia211010112 - 0 4 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 7 of 65 1 - 888 - 824 - 4184 list of tables table 1. ia8044 and ia8344 40 - lead pdip pin listing ................................ .............................. 12 table 2. ia8044 and ia8344 44 - pin plcc pin listing ................................ ............................... 15 table 3. ia8044 and ia8344 absolute maximum ratings ................................ .......................... 17 table 4. ia8044 and ia8344 dc characteristics ................................ ................................ ......... 17 table 5. i nput /o utput characteristics of ic signals ................................ ................................ ..... 19 table 6. r eset vectors ................................ ................................ ................................ .................. 20 table 7. sfr bit addressable locations ................................ ................................ ...................... 22 table 8. internal ram bit addressable locations ................................ ................................ ...... 22 table 9. special function registers ................................ ................................ .............................. 23 table 10. additional functions of port p3 ................................ ................................ ................... 24 table 11. port 0 register ................................ ................................ ................................ .............. 25 table 12. port 1 register ................................ ................................ ................................ .............. 25 table 13. port 2 register ................................ ................................ ................................ .............. 25 table 14. port 3 register ................................ ................................ ................................ .............. 26 table 15. timer mode register ................................ ................................ ................................ .... 27 table 16. timer mode select bits ................................ ................................ ................................ 28 table 17. timer control register ................................ ................................ ................................ . 28 table 18. timer 0 high byte register ................................ ................................ .......................... 29 table 19. timer 0 low byte register ................................ ................................ .......................... 29 table 20. timer 1 high byte register ................................ ................................ .......................... 29 table 21. timer 1 low byte r egister ................................ ................................ .......................... 29 table 22. accumulator register ................................ ................................ ................................ ... 32 table 23. b register ................................ ................................ ................................ ..................... 32 table 24. program status word register ................................ ................................ ..................... 32 table 25. rs1/rs0 bank selections by state ................................ ................................ ............... 33 table 26. stack pointer ................................ ................................ ................................ ................. 33 table 27. data pointer (high) register ................................ ................................ ........................ 33 table 28. data pointer (low) register ................................ ................................ ......................... 33 table 29. interrupt priority register ................................ ................................ ............................. 35 table 30. interrupt enable register ................................ ................................ .............................. 36 table 31. serial mode regis ter ................................ ................................ ................................ .... 37 table 32. serial mode select clock mode bits ................................ ................................ ............ 38 table 33. status/command register ................................ ................................ ............................. 38 table 34. send/receive count register ................................ ................................ ....................... 39 table 35. station address register ................................ ................................ ............................... 40 table 36. transm it buffer start address register ................................ ................................ ........ 40 table 37. transmit buffer length register ................................ ................................ .................. 40 table 38. transmit control byte register ................................ ................................ .................... 41 table 39. receive buffer start address register ................................ ................................ ......... 41 table 40. receive buffer length register ................................ ................................ ................... 41 ?
ia8044/ia8344 data sheet sdlc communicat ions controller march 30, 2010 ia211010112 - 0 4 http://w ww.innovasic.com uncontrolled when pr inted or copied customer support: page 8 of 65 1 - 888 - 824 - 4184 table 41. receive field length register ................................ ................................ ...................... 41 table 42. receive control byte register ................................ ................................ ..................... 42 table 43 . dma count register (dma cnt) ................................ ................................ .............. 42 table 44. dma count register (fifo) ................................ ................................ ........................ 42 table 45. siu state counter ................................ ................................ ................................ ......... 42 table 46. basic sdlc frame ................................ ................................ ................................ ....... 44 table 47. frame format options ................................ ................................ ................................ .. 45 table 48. external program memory characteristics ................................ ................................ ... 50 table 49. external data memory characteristics ................................ ................................ ......... 50 table 50. serial interface characteristic s ................................ ................................ ..................... 51 table 51. external clock drive characteristics ................................ ................................ ........... 51 table 52. reset values register ................................ ................................ ................................ ... 56 table 53. arithmetic operations ................................ ................................ ................................ ... 57 table 54. logic operations ................................ ................................ ................................ ........... 58 table 55. data transfer ................................ ................................ ................................ ................ 59 table 56. boolean manipulation ................................ ................................ ................................ ... 60 table 57. program branches ................................ ................................ ................................ ......... 60 tab le 58. innovasic/intel part number cross - reference for the pdip ................................ ........ 61 table 59. innovasic/intel part number cross - reference for the plcc ................................ ....... 61 table 60. summary of errata ................................ ................................ ................................ ........ 62 table 61. revision history ................................ ................................ ................................ ........... 64 ?
ia8044/ia8344 data sheet sdlc communications controller march 30, 2010 ia211010112 - 0 4 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 9 of 65 1 - 888 - 8 24 - 4184 1. introduction the innovasic semiconductor ia8044 and ia8344 are D plug - and - play drop - in replacement s and are form, fit, and function compatible parts to the intel 8044 and 8344 (see chapter 4, innovasic /intel part number cross - referenc e tables ) . these devices are produced using inno vasics managed ic lifetime extension system (miles?). this cloning technology, which produces replacement ics beyond simple emulations, ensures complete compatibility with the original device, including any Dundocumented features. additionally, the mil es? process captures the clone design in such a way that production of the clone can continue even as silicon technology advances. the ia8044 and ia8344 replace the obsolete intel 8044 and 8344 , allowing users to retain existing board designs, software co mpilers/ assemblers, and emulation tools thus avoiding expensive redesign efforts. the ia8044 and ia8344 are fast single - chip 8 - bit microcontrollers with an integrated sdlc/hdlc serial interface controller. they are fully functional 8 - bit embedded controll ers that execut e all asm51 instructions and have the same instruction set as the intel 80c51. the ia8044 and ia8344 can access the instructions from two types of program memory, serve software and hardware interrupts, and provide interface for serial comm unications and a timer system. the ia8044 and ia8344 are fully compatible with the intel 8x44 series . this data sheet documents all necessary engineeri ng information about the ia8044 and ia8344 including functional and i/o descriptions, electrical chara cteristics, and applicable timing. 1.1 features form, fit , and function compatible with the intel 8044 and 8344 packaging options available in both leaded and rohs versions : C 40 - pin plastic dual in - line package ( pdip ) (see ia8044 40 - lead pdip package diagram ) C 44 - pin plastic leaded chip carrier ( plcc ) (see ia8344 44 - pin plcc package diagram ) 8 - bit control unit (see f unctional block diagram ) 8 - bit arithmetic - logic unit with 16 - bit multiplication and division 12 - mhz clock four 8 - bit input/output ports two 16 - bit timer/counters serial interface unit with sdlc/hdlc compatibility 2.4 - mbps maximum serial data rate two - le vel priority interrupt system 5 interrupt sources internal clock prescaler and phase generator 192 bytes of read/write data memory space 64 - kbyte external program memory space ?
ia8044/ia8 344 data sheet sdlc communications controller march 30, 2010 ia211010112 - 0 4 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 10 of 65 1 - 888 - 824 - 4184 64 - kbyte external data memory space 4 - kbyte internal rom (ia8044 only) 1.2 variants ia8044 C 4 - kbyte internal rom with r0117 version 2.3 firmware C 192 - byte internal ram C 64 - kbyte external program and data space ia8344 C 192 - byte internal ram C 64 - kbyte external program and data space 2. packaging , pin descriptions , and physical dimensions the innov asic semiconductor ia8044 and ia8344 serial controller s are available in the following packages: 40 - pin plastic dual in - line package ( pdip ) , equivalent to original pdip package (see physical package dimensi ons ) 44 - lead plastic leaded chip carrier ( plcc ), equivalent to original plcc package (see physical package dimensions ) ?
ia8044/ia8 344 data sheet sdlc communications controller march 30, 2010 ia211010112 - 0 4 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 11 of 65 1 - 888 - 824 - 4184 2.1 pdip package the pinout for the ia8044 and ia8344 40 pdip package is as shown in fi gure 1 . although figure 1 shows Dia8x44, each device has a complete part number marked on its face (see chapter 8, innovasic/intel part number cross - reference tables ). the corresp onding pinout is p rovided in table 1 . figure 1 . ia8044 and ia8344 40 - lead pdip package diagram ? ( 6 ) p 1 . 5 ( 1 ) p 1 . 0 ( 2 ) p 1 . 1 ( 3 ) p 1 . 2 ( 4 ) p 1 . 3 ( 5 ) p 1 . 4 ( 7 ) ( r t s ) p 1 . 6 ( 8 ) ( 9 ) r s t ( 1 0 ) ( 1 1 ) ( 1 2 ) ( i n t 0 ) p 3 . 2 ( 1 3 ) ( i n t 1 ) p 3 . 3 ( 1 4 ) i a 8 x 4 4 p d i p p 0 . 7 ( a d 7 ) e a a l e p s e n ( 2 0 ) v s s ( 1 5 ) ( s c l k / t 1 ) p 3 . 5 ( 1 6 ) ( w r ) p 3 . 6 ( 1 7 ) ( r d ) p 3 . 7 ( 1 8 ) x t a l 2 ( 1 9 ) x t a l 1 ( 2 1 ) ( 2 2 ) ( 2 3 ) ( 2 4 ) p 2 . 1 ( a 9 ) p 2 . 0 ( a 8 ) ( 4 0 ) ( 3 9 ) ( 3 8 ) ( 3 7 ) ( 3 6 ) ( 3 5 ) ( 3 4 ) ( 3 3 ) ( 3 2 ) ( 3 1 ) ( 3 0 ) ( 2 9 ) ( 2 8 ) ( 2 7 ) ( 2 6 ) ( 2 5 ) ( t 0 ) p 3 . 4 p 2 . 3 ( a 1 1 ) p 2 . 2 ( a 1 0 ) p 2 . 5 ( a 1 3 ) p 2 . 4 ( a 1 2 ) p 2 . 7 ( a 1 5 ) p 2 . 6 ( a 1 4 ) p 0 . 5 ( a d 5 ) p 0 . 6 ( a d 6 ) p 0 . 3 ( a d 3 ) p 0 . 4 ( a d 4 ) p 0 . 1 ( a d 1 ) p 0 . 2 ( a d 2 ) v c c p 0 . 0 ( a d 0 ) ( c t s ) p 1 . 7 ( r x d ) p 3 . 0 ( t x d ) p 3 . 1 ?
ia8044/ia8 344 data sheet sdlc communications controller march 30, 2010 ia211010112 - 0 4 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 12 of 65 1 - 888 - 824 - 4184 table 1 . ia8044 and ia8344 40 - lead pdip pin listing pin name pin name pin name pin name 1 p1.0 11 p3.1 (txd) 21 p2.0 (a8) 31 ea 2 p1.1 12 p3.2 (int0) 22 p2.1 (a9) 32 p0.7 (ad7) 3 p1.2 13 p3.3 (int1) 23 p2.2 (a10) 33 p0.6 (ad6) 4 p1.3 14 p3.4 (t0) 24 p2.3 (a11) 34 p0.5 (ad5) 5 p1.4 15 p3.5 (sclk/t1) 25 p2.4 (a12) 35 p0.4 (ad4) 6 p1.5 16 p3.6 (wr) 26 p2 .5 (a13) 36 p0.3 (ad3) 7 p1.6 (rts) 17 p3.7 (rd) 27 p2.6 (a14) 37 p0.2 (ad2) 8 p1.7 (cts) 18 xtal2 28 p2.7 (a15) 38 p0.1 (ad1) 9 rst 19 xtal1 29 psen 39 p0.0 (ad0) 10 p3.0 (rxd) 20 vss 30 ale 40 vcc ?
ia8044/ia8 344 data sheet sdlc communications controller march 30, 2010 ia211010112 - 0 4 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 13 of 65 1 - 888 - 824 - 4184 2.2 pdip physical dimensions the physica l dimensions for the 40 pdip are as shown in figure 2 . figure 2 . pdip physical package dimensions legend: symbol typical (in inches) a 0.155 a1 0.010 b 0.018 b1 0 .050 c 0.010 d 2.055 e 0 .100 e 0.600 e1 0 . 545 eb 0.650 l 0 .1 30 ? d l a 1 a b b 1 e s i d e v i e w ( l e n g t h ) l e a d 1 i d e n t i f i e r 1 l e a d c o u n t d i r e c t i o n e 1 e t o p e b c s i d e v i e w ( w i d t h )
ia8044/ia8 344 data sheet sdlc communications controller march 30, 2010 ia211010112 - 0 4 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 14 of 65 1 - 888 - 824 - 4184 2.3 plcc package the pinout for the ia80 44 and ia8344 44 plcc package is as shown in figure 3 . although figure 3 shows Dia8x44, each device has a complete part number marked on its face (see chapter 8, innovasic/intel part number cross - reference tables ). the corresponding pinout is provided in table 2 . figure 3 . ia80 44 and ia8344 44 - pin plcc package diagram ? p 1 . 3 p 1 . 4 p 3 . 6 p 2 . 6 ( 1 2 ) n . c . ( 7 ) p 1 . 5 ( 8 ) p 1 . 6 ( 9 ) p 1 . 7 ( 1 0 ) r s t / v p d ( 1 1 ) p 3 . 0 ( 1 3 ) p 3 . 1 ( 1 4 ) p 3 . 2 ( 1 5 ) p 3 . 3 ( 1 6 ) p 3 . 4 ( 1 7 ) p 3 . 5 p 0 . 4 a l e n . c . e a p 0 . 6 p 0 . 5 x t a l 2 p 3 . 7 ( 6 ) ( 5 ) ( 4 ) ( 3 ) ( 2 ) ( 1 ) ( 4 4 ) ( 4 3 ) ( 4 2 ) p 0 . 1 ( 4 1 ) p 0 . 2 ( 4 0 ) p 0 . 3 ( 3 4 ) ( 3 9 ) ( 3 8 ) ( 3 7 ) ( 3 6 ) ( 3 5 ) ( 3 3 ) ( 3 2 ) ( 3 1 ) ( 3 0 ) ( 2 9 ) ( 1 8 ) ( 1 9 ) ( 2 0 ) ( 2 1 ) ( 2 2 ) ( 2 3 ) ( 2 4 ) ( 2 5 ) ( 2 6 ) ( 2 7 ) ( 2 8 ) v c c p 0 . 0 p 1 . 0 n . c . p 1 . 2 p 1 . 1 v s s x t a l 1 p 2 . 0 n . c . p 2 . 2 p 2 . 1 p 2 . 4 p 2 . 3 p 2 . 5 p 2 . 7 p s e n p 0 . 7 i a 8 x 4 4 p l c c ?
ia8044/ia8 344 data sheet sdlc communications controller march 30, 2010 ia211010112 - 0 4 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 15 of 65 1 - 888 - 824 - 4184 table 2 . ia80 44 and ia8344 44 - pin plcc pin listing pin name pin name pin name pin name 1 n.c. 12 n.c. 23 n.c. 34 n.c. 2 p1.0 13 p3.1 24 p2.0 35 ea 3 p1.1 14 p3.2 25 p2.1 36 p0.7 4 p1.2 15 p3.3 26 p2.2 37 p0.6 5 p1.3 16 p3.4 27 p2.3 38 p0.5 6 p1.4 17 p3.5 28 p2.4 39 p0.4 7 p1.5 18 p3.6 29 p2.5 40 p0.3 8 p1.6 19 p3.7 30 p2.6 41 p0.2 9 p1.7 20 xtal2 31 p2.7 42 p0.1 10 rst/vpd 21 xtal1 32 psen 43 p0.0 11 p3.0 22 vss 33 ale 44 vcc ?
ia8044/ia8 344 data sheet sdlc communications controller march 30, 2010 ia211010112 - 0 4 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 16 of 65 1 - 888 - 824 - 4184 2.4 plcc physical dimensi ons the physical dimensions for the 44 plcc are as shown in figure 4 . figure 4 . plcc physical package dimensions legend: symbol typical (in inches) a 0.180 a1 0.110 d1 0.653 d2 0.610 d3 0.500 e1 0.653 e2 0.610 e3 0.500 e 0.050 d 0.690 e 0.690 ? d 3 e 3 p i n 1 i d e n t i f i e r & z o n e 0 . 0 4 5 * 4 5 t o p v i e w d d 1 e e 1 b o t t o m v i e w 0 . 0 0 4 0 . 0 2 m i n . r 0 . 0 3 5 a 1 e 0 . 0 2 6 C 0 . 0 3 2 a 0 . 0 1 3 C 0 . 0 2 1 d 2 / e 2 s i d e v i e w s e a t i n g p l a n e
ia8044/ia8 344 data sheet sdlc communications controller march 30, 2010 ia211010112 - 0 4 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 17 of 65 1 - 888 - 824 - 4184 3. maximum ratings and d c characteristics t he ia8044/ia8344 absolute maximum ratings and dc characteristics are provided in tables 3 and 4, respectively. table 3 . ia8044 and ia83 44 absolute maximum ratings parameter rating ambient temperature under bias ? 40c to +85c storage temperature ? 40c to +150c power supply (v dd ) ? 0.3 to +6vdc voltage on any pin to vss ? 0.3 to (v dd +0.3) a power dissipation 2w a this devi ce does not contain eprom or it s related programming circuitry. therefore , this limit mus t be adhered to especially for input pin ea, which is used as the programming voltage pin in the intel device. exceeding the listed maximum voltage will cause damage to the device. table 4 . ia8044 and ia8344 dc characteristics sym bol parameter min typ max unit vil input low voltage C C 0.8 v vih input high voltage 2.0 C C v vol output low voltage (iol= 4ma) C C 0.4 v voh output high voltage (ioh= 4ma) 3.5 C C v rpu pull - up resistance (ports 1, 2, 3) C 50 C kw rpd pull - down re sistance (rst) C 50 C kw iil input low current (ports 1, 2, 3) ? 2 00 C 1 a iil1 input low current ( po, ea ) ? 1 C 1 a iih input high current (rst) ? 1 C 2 00 a iih1 input high current ( po, ea ) ? 1 C 1 a ioz tri - state leakage current (port 0) ? 10 C 10 a icc power supply current (@ 12 mhz) C C 50 ma cio pin capacitance C 4 C pf 4. functional description 4.1 functional block diagram a functional block diagram of the ia8044 and ia8344 is shown in figure 5 . descriptions of the functional modules are provided in the following subsections. ?
ia8044/ia8 344 data sheet sdlc communications controller march 30, 2010 ia211010112 - 0 4 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 18 of 65 1 - 888 - 824 - 4184 figure 5 . functional block diagram ? p o r t 3 s p c l f u n c / i o p o r t 1 s p c l f u n c / i o p o r t 2 a d d r / d a t a / i o p o r t 0 a d d r / d a t a / i o 1 9 2 x 8 d u a l p o r t r a m s i u c o n t r o l x t a l r e s e t i / o f o r m e m o r y , s i u , d m a , i n t e r r u p t s , a n d t i m e r s c l o c k g e n . & t i m i n g c 8 0 5 1 c p u i n t e r r u p t s t i m e r s a d d r e s s / d a t a m e m o r y c o n t r o l
ia8044/ia8 344 data sheet sdlc communications controller march 30, 2010 ia211010112 - 0 4 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 19 of 65 1 - 888 - 824 - 4184 4.2 input/output characteristics table 5 describes the i/o characteristics for each signal on the ic. the signal names correspond to those on the pinout diagrams pro vided . the table provides the i/o description of the ia8044 and the ia8344. table 5 . i nput /o utput characteristics of ic signals name type description rst i reset this pin will cause the chip to reset when held high for two machin e cycles while the oscillator is running. ale o address latch enable used to latch the address on the falling edge for external memory accesses. psen o program store enable when low , acts as an output enable for external program memory. ea i external ac c ess when held low , ea will cause the ia8044/ia8344 to fetch instructions from external memory. p0.7 C p0.0 i/o port 0 8 - bit i/o port and low order multiplexed address/data byte for external accesses. p1. 7 C p1.0 i/o port 1 8 - bit i/o port. two bits have alt ernate functions, p1.6 (rts) and p1.7 (cts). p2.7 C p2.0 i/o port 2 8 - bit i/o port. it also functions as the high order address byte during external accesses. p3.7 C p3.0 i/o port 3 8 - bit i/o port. port 3 bits also have alternate functions as described bel ow. p3.0 ( rxd ) receive s data input for siu or direction control for p3.1 dependent upon data link configuration. p3.1 (txd) transmit s data output for siu or data input/output dependent upon data link configuration. also enables diagnostic mode when cleare d. p3.2 (int0) interrupt 0 input or gate control input for counter 0. p3.3 ( int1 ) interrupt 1 input or gate control input for counter 1. p3.4 ( t0 ) input to counter 0. p3.5 (sclk/t1) sclk input to siu or input to counter 1. p3.6 ( wr ) external memory write s ignal. p3.7 ( rd ) external memory read signal. xtal1 i crystal input 1 connect s to vss when external clock is used on xtal2. may be conn ected to a crystal (with xtal2) or may be driven directly with a clock source (xtal2 not connected). xtal2 o crystal i nput 2 may be conn ected to a crystal (with xtal1) or may be driven directly with an inverted clock source (xtal1 tied to ground). vss p ground. vcc p +5v power. ?
ia8044/ia8 344 data sheet sdlc communications controller march 30, 2010 ia211010112 - 0 4 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 20 of 65 1 - 888 - 824 - 4184 4.3 memory organization 4.3.1 program memory program memory includes interrupt and reset vectors. th e interrupt vectors are spaced at 8 - byte intervals, starting from 0003h for external interrupt 0. table 6 . reset vectors location service 0003h external interrupt 0 000bh timer 0 overflow 0013h extern al interrupt 1 001bh ti mer 1 overflow 0023h siu interrupt these locations may be used for program code, if the corresponding interrupts are not used (disabled). the program memory space is 64k, from 0000h to ffffh. the lowest 4k of program code (0000h to 0fffh) can be fetc hed from external or internal program memory. this selection is made by strapping pin Dea (external address) to gnd or vcc. if during reset Dea is held low, all the program code is fetched from external memory. if during reset Dea is held high, the l owest 4k of program code (0000h to 0fffh) is fetched from internal memory (rom). program memory addresses above 4k (0fffh) will cause the program code to be fetched from external memory regardless of the setting of Dea. 4.3.2 external data memory the ia8044/ia 8344 microcontroller core incorporates the harvard architecture, with separate code and data spaces. the code from external memory is fetched by Dpsen strobe, while data is read from ram by bit [7] of p3 (read strobe) and written to ram by bit [6] of p3 (write strobe). the external data memory space is active only by addressing through use of the movx instruction and the 16 - bit data pointer register (dptr). a smaller subset of external data memory (8 - bit addressing) may be accessed by using the movx ins truction with register indexed addressing. 4.3.3 internal data memory as presented in figure 6 , the internal data memory address is always one byte wide. the memory space is 192 bytes large (00h to bfh), and can be accessed by either direct or indirect addressi ng. the special function registers (sfrs) occupy the upper 128 bytes. this sfr area is available only by direct addressing. internal memory that overlaps the sfr address space is only accessible by indirect addressing. ?
ia8044/ia8 344 data sheet sdlc communications controller march 30, 2010 ia211010112 - 0 4 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 21 of 65 1 - 888 - 824 - 4184 figure 6 . internal data memory addresses 00h to ffh ? 8 0 h f f h 8 0 h b f h i n d i r e c t a d d r e s s i n g r a m 0 0 h 0 7 h 0 8 h 1 7 h 1 8 h 1 f h 2 0 h 2 f h 3 0 h 7 f h 1 0 h 0 f h r e g i s t e r b a n k 0 r e g i s t e r b a n k 1 r e g i s t e r b a n k 2 r e g i s t e r b a n k 3 b i t a d d r e s s a b l e m e m o r y i n t e r n a l d a t a r a m d i r e c t a d d r e s s i n g s p e c i a l f u n c t i o n r e g i s t e r s ( s f r s ) a d d r e s s a b l e b i t s i n s f r s ( 1 2 8 b i t s )
ia8044/ia8 344 data sheet sdlc communications controller march 30, 2010 ia211010112 - 0 4 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 22 of 65 1 - 888 - 824 - 4184 4.3.4 bit addressable memory both the internal ram and the sfrs have locations that are bit addressable in addition to the byte addressable locations (see tables 7 and 8 ) . table 7 . sfr bit addressable locations byte address bit [ 7 ] bit [ 6 ] bit [ 5 ] bit [ 4 ] bit [ 3 ] bit [ 2 ] bit [ 1 ] bit [ 0 ] register f0h f7h f6h f5h f4h f3h f2h f1h f0h b e0h e7h e6h e5h e4h e3h e2h e1h e0h acc d8h dfh deh ddh dch dbh dah d9h d8h nsnr d0h d7h d6h d5h d4h d3h d 2h d1h d0h psw c8h cfh ceh cdh cch cbh cah c9h c8h sts b8h C C C bch bbh bah b9h b8h ip b0h b7h b6h b5h b4h b3h b2h b1h b0h p3 a8h afh C C ach abh aah a9h a8h ie a0h a7h a6h a5h a4h a3h a2h a1h a0h p2 90h 97h 96h 95h 94h 93h 92h 91h 90h p1 88h 8fh 8 eh 8dh 8ch 8bh 8ah 89h 88h tcon 80h 87h 86h 85h 84h 83h 82h 81h 80h p0 table 8 . internal ram bit addressable locations byte address bit [ 7 ] bit [ 6 ] bit [ 5 ] bit [ 4 ] bit [ 3 ] bit [ 2 ] bit [ 1 ] bit [ 0 ] 30h - bfh upper internal ram loca tions 2fh 7fh 7eh 7dh 7ch 7bh 7ah 79h 78h 2eh 77h 76h 75h 74h 73h 72h 71h 70h 2dh 6fh 6eh 6dh 6ch 6bh 6ah 69h 68h 2ch 67h 66h 65h 64h 63h 62h 61h 60h 2bh 5fh 5eh 5dh 5ch 5bh 5ah 59h 58h 2ah 57h 56h 55h 54h 53h 52h 51h 50h 29h 4fh 4eh 4dh 4ch 4bh 4ah 49h 48h 28h 47h 46h 45h 44h 43h 42h 41h 40h 27h 3fh 3eh 3dh 3ch 3bh 3ah 39h 38h 26h 37h 36h 35h 34h 33h 32h 31h 30h 25h 2fh 2eh 2dh 2ch 2bh 2ah 29h 28h 24h 27h 26h 25h 24h 23h 22h 21h 20h 23h 1fh 1eh 1dh 1ch 1bh 1ah 19h 18h 22h 17h 16h 15h 14h 13h 12h 11h 10h 21h 0fh 0eh 0dh 0ch 0bh 0ah 09h 08h 20h 07h 06h 05h 04h 03h 02h 01h 00h 18h - 1fh register bank 3 10h - 17h register bank 2 08h - 0fh register bank 1 00h - 07h register bank 0 ?
ia8044/ia8 344 data sheet sdlc communications controller march 30, 2010 ia211010112 - 0 4 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 23 of 65 1 - 888 - 824 - 4184 4.4 special function registers table 9 presents the sfrs of the ia8044 a nd ia8344. table 9 . special function registers symbol register description byte address (hex) bit addresses (hex) (msb C lsb) acc accumulator e0h e7h C e0h b b register f0h f7h C f0h psw program status word d0h d7h C d0h sp stack po inter 81h C dph data pointer high byte 82h C dpl data pointer low byte 83h C p0 port 0 80h 87h C 80h p1 port 1 90h 97h C 90h p2 port 2 a0h a7h C a0h p3 port 3 b0h b7h C b0h ip interrupt priority b8h bch C b8h ie interrupt enable a8h afh,ach C a8h tmod t imer/counter mode 89h C tcon timer/counter control 88h 8fh C 88h th0 timer/counter 0 high byte 8ch C tl0 timer/counter 0 low byte 8ah C th1 timer/counter 1 high byte 8dh C tl1 timer/counter 1 low byte 8bh C smd serial mode c9h C sts siu status and co mmand c8h cfh C c8h nsnr siu send/receive count d8h dfh C d8h stad siu station address ceh C tbs transmit buffer start address dch C tbl transmit buffer length dbh C tcb transmit control byte dah C rbs receive buffer start address cch C rbl receive bu ffer length cbh C rfl receive field length cdh C rcb receive control byte cah C dma cnt dma count cfh C fifo fifo contents (3 bytes) df,de,ddh C siust siu state counter d9h C ?
ia8044/ia8 344 data sheet sdlc communications controller march 30, 2010 ia211010112 - 0 4 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 24 of 65 1 - 888 - 824 - 4184 4.5 ports ports p0, p1, p2, and p3 are sfrs. the contents of the sfr can be observed on corresponding pins on the chip. writing a D1 to any of the ports causes the corresponding pin to be at high level (vcc), and writing a D0 causes the corresponding pin to be held at low level (gnd). all four ports on the chip are bi - direction al. each of them consists of a latch (sfr p0 to p3), an output driver, and an input buffer, so the cpu can output or read data through any of these ports if they are not used for alternate purposes. ports p0, p1, p2, and p3 can perform some alternate func tions. ports p0 and p2 are used to access external memory. in this case, port Dp0 outputs the multiplexed lower eight bits of address with Dale strobe high and then reads/writes eight bits of data. port p2 outputs the higher eight bits of address. ke eping Dea pin low (tied to gnd) activates this alternate function for ports p0 and p2. port p3 and p1 can perform some alternate functions. the pins of port p3 are multifunctional. they can perform the additional functions described in table 1 0 . table 10 . additional functions of port p3 pin symbol function p3.0 rxd, i/o in point - to - point or multipoint configurations (smd.3 = 0) this pin is i/o and signals the direction of data flow on data (p3.1). in loop mode (smd.3 = 1) and diagnostic mode this pin is rxd, receive data input. p3.1 txd, data in point - to - point or multipoint configurations (smd.3 = 0) this pin is data and is the transmit/receive data pin. in loop mode (smd.3 = 1) thi s pin is the transmit data, txd pin. writi ng a D 0 to this port buffer bit enables the diagnostic mode. p3.2 int0 external interrupt 0 input. also gate control input for counter 0. p3.3 int1 external interrupt 1 input. also gate control input for counter 1. p3.4 t0 timer/counter 0 exter nal input. setting the appropriate bits in the special function registers tcon and tmod activates this function. p3.5 t1, sclk timer/counter 1 external input. setting the appropriate bits in the sfrs tcon and tmod activates this function. can also fun ction as the external clock source for the siu. p3.6 wr external data memory write strobe, active low. this function is activated by a cpu write access to external data memory (i.e. , movx @dptr, a). p3.7 rd external data memory read strobe, active l ow. this function is activated by a cpu read access from external data memory (i.e. , movx a, @dptr). p1.6 rts request to send output, active low. p1.7 cts clear to send input, active low. 4.6 port registers 4.6.1 port 0 (p0) table 1 1 presents the values for por t 0 (p0), a general purpose, 8 - bit, i/o port and multiplexed low order address and data bus with open - drain output buffers. ?
ia8044/ia8 344 data sheet sdlc communications controller march 30, 2010 ia211010112 - 0 4 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 25 of 65 1 - 888 - 824 - 4184 table 11 . port 0 register 7 6 5 4 3 2 1 0 p0.7 p0.6 p0.5 p0.4 p0.3 p0.2 p0.1 p0.0 4.6.2 port 1 (p1) table 1 2 p resents the values for port 1 (p1), a general purpose, eight - bit, i/o port with pullups and auxiliary functions. table 12 . port 1 register 7 6 5 4 3 2 1 0 cts/p1.7 rts/p1.6 p1.5 p1.4 p1.3 p1.2 p1.1 p1.0 b it [7] p1.7/clear to sen d input bit [6] p1.6/request to send output bit [5] p1.5 bit [4] p1.4 bit [3] p1.3 bit [2] p1.2 bit [1] p1.1 bit [0] p1.0 4.6.3 port 2 (p2) table 1 3 presents the values for port 2, a general purpose, 8 - bit, i/o port with pullups and high order address bus. table 13 . port 2 register 7 6 5 4 3 2 1 0 p2.7 p2.6 p2.5 p2.4 p2.3 p2.2 p2.1 p2.0 4.6.4 port 3 (p3) table 1 4 presents the values for port 2, a general purpose, 8 - bit i/o port with pullups and auxiliary functions. bits on this port also fu nction as the siu data transmit/receive i/o, external interrupt inputs, timer inputs and the read and write strobes for external memory accesses. ?
ia8044/ia8 344 data sheet sdlc communications controller march 30, 2010 ia211010112 - 0 4 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 26 of 65 1 - 888 - 824 - 4184 table 14 . port 3 register 7 6 5 4 3 2 1 0 rd wr t1 t0 int1 int0 txd rxd bit [7] rd (p3.7) external data memory read strobe, active low bit [6] wr (p3.6) external data memory write strobe, active low bit [5] t1 (p3.5) timer/counter 1 external input bit [4] t0 (p3.4) timer/counter 0 external input bit [3] int1 (p3.3) external int errupt 1 bit [2] int0 (p3.2) external interrupt 0 bit [1] txd (p3.1) serial output pin bit [0] rxd (p3.0) serial input pin 4.7 timers/counters 4.7.1 timers 0 and 1 the ia8x44 has two 16 - bit timer/counter registers, timer 0 and timer 1. both can be configured for counter or timer operations. in timer mode, the register is incremented every machine cycle, which means that it counts up after every 12 oscillator periods. in counter mode, the register is incremented when the falling edge is observed at the corre sponding input pin t0 or t1. because it takes two machine cycles to recognize a 1 - to - 0 event, the maximum input count rate is 1/24 of the oscillator frequency. there are no restrictions on the duty cycle, however to ensure proper recognition of 0 or 1 st ate, an input should be stable for at least one machine cycle (12 clock periods). four operating modes can be selected for timer 0 and timer 1. two sfrs (tmod and tcon) are used to select the appropriate mode. 4.7.2 mode 0 in mode 0 the timers operate as an 8 - b it timer (th0/1) with a divide by 32 - bit prescalar (tl0/1). mode 0 uses all eight bits of th0/1 and the lower five bits of tl0/1. the upper three bits of tl0/1 are unknowns. setting tr0/1 does not reset the registers th0/1 and tl0/1. as the timer rolls over from all 1s to all 0s it will set the interrupt flag tf0/1. ?
ia8044/ia8 344 data sheet sdlc communications controller march 30, 2010 ia211010112 - 0 4 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 27 of 65 1 - 888 - 824 - 4184 4.7.3 mode 1 mode 1 is the same as mode 0 except that all eight bits of tl0/1 are used instead of just the lower five bits. 4.7.4 mode 2 mode 2 configures tl0/1 as an 8 - bit counter with automatic reloa d from the contents of th0/1. overflow of tl0/1 causes the interrupt tf0/1 to be set and the reload to occur. the contents of th0/1 are not affected by the reload. 4.7.5 mode 3 mode 3 creates two separate 8 - bit counters from tl0 and th0. tl0 uses the timer 0 mode bits from tmod, tmod.0 through tmod.3. th0 is a timer only (not a counter) and uses timer 1s control bits, tr1 and tf1, for operation. timer 1 can still be used if an interrupt is not required by switching it in and out of its own mode 3. with tmo d.4 and tmod.5 both high, timer 1 will stop and hold its count. 4.7.6 timer mode (tmod) table 1 5 presents the values for the timer mode register, which contains bits that select the mode that the timers are to be operated in. the lower nibble controls timer 0 a nd the upper nibble controls timer 1. table 1 6 presents the timer mode select bits. table 15 . timer mode register 7 6 5 4 3 2 1 0 gate c/t m1 m0 gate c/t m1 m0 bit [7] gate (tmod.7) if set, enables external gate control for c ounter/timer 1 (pin int1 for counter 1). when int1 is high, and tr1 bit is set (see tcon register), the counter is incremented every falling edge on t1 input pin. bit [6] c/t (tmod.6) c/t selects timer 1 or counter 1 operation. when set to 1, the count er operation is performed. when cleared to 0, the register will function as a timer. bit [5] m1 (tmod.5) timer 1 mode selector bit. bit [4] m0 (tmod.4) timer 1 mode selector bit. bit [3] gate (tmod.3) if set, enables external gate control for coun ter/timer 0 (pin int0 for counter 0). when int0 is high, and tr0 bit is set (see tcon register), the counter is incremented every falling edge on t0 input pin. ?
ia8044/ia8 344 data sheet sdlc communications controller march 30, 2010 ia211010112 - 0 4 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 28 of 65 1 - 888 - 824 - 4184 bit [2] c/t (tmod.2) c/t selects timer 0 or counter 0 operation. when set to 1, the counter operation is performed. when cleared to 0, the register will function as a timer. bit [1] m1 (tmod.1) timer 0 mode selector bit. bit [0] m0 (tmod.0) timer 0 mode selector bit. table 16 . timer mode select bits m1 m0 operating m ode 0 0 0 13 - bit timer 0 1 1 16 - bit timer/counter 1 0 2 8 - bit auto - reload timer/counter 1 1 3 timer 0 C tl0 is a standard 8 - bit timer/counter controlled by timer 0 control bits. th0 is an 8 - bit timer function only, controlled by timer 1 control bits. 1 1 3 timer/counter 1 stopped and holds its count. can be used to start/stop timer 1 when timer 0 is in mode 3. 4.7.7 timer control (tcon) table 17 presents the timer control register, which provides control bits that start and stop the counters. it also cont ains bits to select the type of external interrupt desired, edge or level. additionally, tcon contains status bits showing when a timer overflows and when an interrupt edge has been detected. table 17 . timer control register 7 6 5 4 3 2 1 0 tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 bit [7] tf1 (tcon.7) timer 1 overflow flag set by hardware when timer 1 overflows. this flag should be cleared by software. in mode 3 this bit is controlled by th0. bit [6] tr1 (tcon.6) timer 1 run control bit. if cleared, timer 1 stops. in mode 3 this bit con trols th0. bit [5] tf0 (tcon.5) timer 0 overflow flag set by hardware when timer 0 overflows. this flag should be cleared by software. bit [4] tr0 (tcon.4) timer 0 run control bit. if cleared, timer 0 stops. bit [3] ie1 (tcon.3) interrupt 1 edge fla g. set by hardware, when falling edge on external pin int1 is detected cleared when interrupt is processed. ?
ia8044/ia8 344 data sheet sdlc communications controller march 30, 2010 ia211010112 - 0 4 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 29 of 65 1 - 888 - 824 - 4184 bit [2] it1 (tcon.2) interrupt 1 type control bit. selects falling edge or low level on input pin to cause interrupt. bit [1] ie0 (tcon.1) inter rupt 0 edge flag. set by hardware, when falling edge on external pin int1 is observed. cleared when interrupt is processed. bit [0] it0 (tcon.0) interrupt 0 type control bit. selects falling edge or low level on input pin to cause interrupt. 4.7.8 timer 0 hi gh byte (th0) table 18 presents the high - order byte of timer/counter 0. table 18 . timer 0 high byte register 7 6 5 4 3 2 1 0 th0.7 th0.6 th0.5 th0.4 th0.3 th0.2 th0.1 th0.0 4.7.9 timer 0 low byte (tl0) table 19 presents the low - order byte of timer/counter 0. table 19 . timer 0 low byte register 7 6 5 4 3 2 1 0 tl0.7 tl0.6 tl0.5 tl0.4 tl0.3 tl0.2 tl0.1 tl0.0 4.7.10 timer 1 high byte (th1) table 2 0 presents the high - order byte of timer/counter 1. table 20 . timer 1 high byte register 7 6 5 4 3 2 1 0 th1.7 th1.6 th1.5 th1.4 th1.3 th1.2 th1.1 th1.0 4.7.11 timer 1 low byte (tl1) table 2 1 presents the low order byte of timer/counter 1. table 21 . timer 1 low byte register 7 6 5 4 3 2 1 0 tl1.7 tl1.6 tl1.5 tl1.4 tl1.3 tl1.2 tl1.1 tl1.0 ?
ia8044/ia8 344 data sheet sdlc communications controller march 30, 2010 ia211010112 - 0 4 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 30 of 65 1 - 888 - 824 - 4184 4.7.12 timer/counter configuration figures 7, 8, 9, and 10 present the configurations of timer 0 mode 0, timer 0 mode 1, timer 0 mode 2, and timer 0 mode 3, respectively. figure 7 . timer 0 mode 0 figure 8 . timer 0 mode 1 ? o s c t l o ( 5 b i t s ) t h 0 ( 8 b i t s ) t f 0 = 1 & 1 i n t e r r u p t p 3 . 4 / t 0 g a t e p 3 . 2 / i n t 0 t r 0 c o n t r o l 1 t c / 0 t c / 1 2 o s c t l o ( 8 b i t s ) t h 0 ( 8 b i t s ) t f 0 = 1 & 1 i n t e r r u p t p 3 . 4 / t 0 g a t e p 3 . 2 / i n t 0 t r 0 c o n t r o l 1 t c / 0 t c / 1 2
ia8044/ia8 344 data sheet sdlc communications controller march 30, 2010 ia211010112 - 0 4 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 31 of 65 1 - 888 - 824 - 4184 figure 9 . timer 0 mode 2 figure 10 . timer 0 mode 3 ? o s c = 1 & 1 p 3 . 4 / t 0 g a t e p 3 . 2 / i n t 0 t r 0 c o n t r o l 1 t c / 0 t c / 1 2 t l o ( 8 b i t s ) t h 0 ( 8 b i t s ) t f 0 i n t e r r u p t r e l o a d o s c = 1 & 1 p 3 . 4 / t 0 g a t e p 3 . 2 / i n t 0 t r 0 c o n t r o l 1 t c / 0 t c / 1 2 t l o ( 8 b i t s ) t f 0 i n t e r r u p t t h 0 ( 8 b i t s ) t f 1 1 / 1 2 f o s c t r 1 c o n t r o l i n t e r r u p t 1 / 1 2 f o s c
ia8044/ia8 344 data sheet sdlc communications controller march 30, 2010 ia211010112 - 0 4 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 32 of 65 1 - 888 - 824 - 4184 4.8 general cpu registers 4.8.1 accumulator (acc) table 2 2 presents the accumulato r register. most instructions use the accumulator to hold the operand. the mnemonics for accumulator - specific instructions refer to accumulator as a, not acc. table 22 . accumulator register 7 6 5 4 3 2 1 0 acc.7 acc.6 acc.5 acc. 4 acc.3 acc.2 acc.1 acc.0 4.8.2 b register (b) table 2 3 presents the b register, which is used during multiply and divide instructions. it can also be used as a scratch - pad register to hold temporary data. table 23 . b register 7 6 5 4 3 2 1 0 b.7 b.6 b.5 b.4 b.3 b.2 b.1 b.0 4.8.3 program status word (psw) table 2 4 presents program status word, which contains cpu status flags, register select bits, and user flags. table 24 . program status word register 7 6 5 4 3 2 1 0 cy ac f0 rs1 rs0 ov C p bit [7] cy (psw.7) carry flag f or carry out of or into bit [7] bit [6] ac (psw.7) auxiliary carry flag f or carry out of or into bit [3] bit [5] f0 (psw.7) general pu rpose flag 0 available for user bit [4] rs1 (psw.7) register bank select control bit [1], used to select working register bank bit [3] rs0 (psw.7) register bank select control bit [0], used to select working register bank ?
ia8044/ia8 344 data sheet sdlc communications controller march 30, 2010 ia211010112 - 0 4 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 33 of 65 1 - 888 - 824 - 4184 bit [2] ov (psw.7) overflow flag bi t [1] (psw.7) user defined flag bit [0] p (ps w.7) parity flag, affected by hardware to indicate odd/even number of Done bits in the accumulator (i.e., even parity) the state of bits rs1 and rs0 selects the working registers bank as presented in table 2 5 . table 25 . rs1/rs0 ba nk selections by state rs1/rs0 bank selected location 00 bank 0 (00h C 07h) 01 bank 1 (08h C 0fh) 10 bank 2 (10h C 17h) 11 bank 3 (18h C 1fh) 4.8.4 stack pointer (sp) table 26 presents the stack pointer, which is a 1 - byte register initialized to 07h after reset. this register is incremented before push and call instructions, causing the stack to begin at location 08h. the stack pointer points to a location in internal ram. table 26 . stack pointer 7 6 5 4 3 2 1 0 sp.7 sp.6 sp.5 sp.4 sp.3 sp.2 sp.1 sp.0 4.8.5 data pointer (dptr) the data pointer (dptr) is two bytes wide. table 27 presents the highest, which is dph. table 28 presents the lower part, dpl. it can be loaded as a 2 - byte register (mov dptr,#data16) or as two registers (mov dpl,#da ta8 each). it is generally used to access external code (movc a,@a+dptr each) or data space (mov a,@dptr). table 27 . data pointer (high) register 7 6 5 4 3 2 1 0 dph.7 dph.6 dph.5 dph.4 dph.3 dph.2 dph.1 dph.0 table 28 . data pointer (low) register 7 6 5 4 3 2 1 0 dpl.7 dpl.6 dpl.5 dpl.4 dpl.3 dpl.2 dpl.1 dpl.0 ?
ia8044/ia8 344 data sheet sdlc communications controller march 30, 2010 ia211010112 - 0 4 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 34 of 65 1 - 888 - 824 - 4184 4.9 interrupts the ia8044/ia8344 provides five interrupt sources. there are two external interrupts accessible through pins int0 and int1, edge or level sensitive (falling edge or low level). there are also internal interrupts associated with timer 0 and timer 1 and an internal interrupt from the siu. 4.9.1 external interrupts the choice between external interrupt level or transition activity is made by setting it1 and it0 bits in the sfr tcon. when the interrupt event happens, a corresponding interrupt control bit is set (it0 or it1). this control bit triggers an interrupt if the appropriate interrupt bit is enabled. when the interrupt service routine is vectored, the corresponding control bit (it0 or it1) is cleared, provided that the edge triggered mode was selected. if level mode is active, the external requesting source controls flags it0 or it1 by the logic level on pins int0 or int1 (0 or 1). 4.9.2 timer 0 and timer 1 interrupts timer 0 and 1 interrupts are generated by tf0 and tf1 flags, which are set by the rollover of timers 0 and 1, respectively. when an interrupt is generated, the flag that caused this interrupt is cleared by the hardware if th e cpu accessed the corresponding interrupt service vector. this can be done only if this interrupt is enabled in the ie register. 4.9.3 serial interface unit interrupt the siu generates an interrupt when a frame is received or transmitted. no interrupts are ge nerated for a received frame with errors. 4.9.4 interrupt priority level structure there are two priority levels in the ia8044/ia8344 any interrupt can be individually programmed to a high or low priority level. modifying the appropriate bits in the sfr ip can accomplish this. a low - priority interrupt service routine will be interrupted by a high - priority interrupt. however, the high - priority interrupt cannot be interrupted. if two interrupts of the same priority level occur, an internal polling sequence deter mines which will be processed first. this polling sequence is a second priority structure defined as follows: ie0 1 highest tf0 2 ie1 3 tf1 4 siu lowest ?
ia8044/ia8 344 data sheet sdlc communications controller march 30, 2010 ia211010112 - 0 4 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 35 of 65 1 - 888 - 824 - 4184 4.9.5 interrupt handling the interrupt flags are sampled during each machine cycle. the samples are polled during the next machine cycle. if an interrupt flag is captured, the interrupt system will generate an lcall instruction to the appropriate service routine, provided that this is not disabled by the following conditions: an interrupt of the same or higher priority is processed . the current machine cycle is not the last cycle of the instruction (the instruction cannot be interrupted). the instruction in progress is reti or any write to ie or ip registers. note: if an interrupt is disabled and the interrupt flag is cleared before the blocking condition is removed, no interrupt will be generated because the polling cycle will not sample any active interrupt condition. in other words, the interrupt condition is not remembered; every polling cycle is new. 4.9.6 inte rrupt priority register (ip) this register sets the interrupt priority to high or low for each interrupt. when the bit is set, it selects high priority. within each level the interrupts are prioritized as follows: external interrupt 0 timer/counter 0 ext ernal interrupt 1 timer/counter 1 siu an interrupt process routine cannot be interrupted by an interrupt of lesser or equal priority (see table 29 ). table 29 . interrupt priority register 7 6 5 4 3 2 1 0 C C C ps pt1 px1 pt0 px0 bit [7] (ip.7) bit [6] (ip.6) bit [5] (ip.5) bit [4] ps (i p.4) siu interrupt priority bit ?
ia8044/ia8 344 data sheet sdlc communications controller march 30, 2010 ia211010112 - 0 4 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 36 of 65 1 - 888 - 824 - 4184 bit [3] pt1 (ip.3) timer 1 interrupt priority bit bit [2] px1 (ip.2) external inte rrupt 1 interrupt priority bit bit [1] pt0 (ip.1) timer 0 inter rupt priority bit bit [0] px0 (ip.0) external int errupt 0 interrupt priority bit 4.9.7 interrupt enable register (ie) table 30 presents the interrupt enable register, which contains the global interrupt enable bit and individual interrupt enable bits. setting a bit enables the corresponding interrupt. table 30 . interrupt enable register 7 6 5 4 3 2 1 0 ea C C es et1 ex1 et0 ex0 bit [7] ea (pc on.7) enable all interrupts bit bit [6] (pcon.6) bit [5] (pcon.5) bit [4] es (pcon.4) siu interrupt enable bit bit [3] et1 (pcon. 3) timer 1 interrupt enable bit bit [2] ex1 (pcon.2) external i nterrupt 1 interrupt enable bit bit [1] et0 (pcon. 1) timer 0 interrupt enable bit bit [0] ex0 (pcon.7) external interrupt 0 interrupt enable bit 4.10 siu serial interface unit the siu is a serial interface customized to support sdlc/hdlc protocol. as such, it supports zero bit insertion/deletion, flags automati c access recognition and a 16 - bit crc. the siu has two modes of operation auto and flexible. the auto mode uses a subset of the sdlc protocol implemented in hardware. this frees the cpu from having to respond to every frame but limits the frame types. in the flexible mode every frame is under cpu control and therefore more options are available. the siu is controlled by and communicates to the cpu by using several sfrs. data transmitted by or received by the siu is stored in the 192 - byte internal ram in blocks referred to as the transmit and receive buffers. the siu can support operation in one of ?
ia8044/ia8 344 data sheet sdlc communications controller march 30, 2010 ia211010112 - 0 4 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 37 of 65 1 - 888 - 824 - 4184 three serial data link configurations, 1) half - duplex, point - to - point, 2) half - duplex, multipoint, or 3) loop mode. 4.10.1 siu special function registers the cpu c ontrols the siu and receives status from the siu via 11 sfrs. the serial interface unit control registers are detailed in the sections that follow. 4.10.2 serial mode register (smd) table 3 1 presents the serial mode register, which sets the operational mode of t he siu. the cpu can read and write smd. the siu can read smd. to prevent conflicts between cpu and siu, accesses to smd the cpu should write smd only when rts and rbe bits in the sts register are both zero. smd is normally only accessed during initiali zation. this register is byte addressable. table 3 2 presents the serial mode select clock mode bits . table 31 . serial mode register 7 6 5 4 3 2 1 0 scm2 scm1 scm0 nrzi loop pfs nb nfcs bit [7] scm2 (smd.7) select clock mode bit [2]. bit [6] scm1 (smd.6) select clock mode bit [1]. bit [5] scm0 (smd.5) select clock mode bit [0]. bit [4] nrzi (smd.4) when set selects nrzi encoding otherwise nrz. bit [3] loop (smd.3) when set, selects loop conf iguration, else point - to - point mode. bit [2] pfs (smd.2) pre - frame sync mode. when set, causes two bytes to be transmitted before the first flag of the frame for dpll synchronization. if nrzi is set, 00h is transmitted, otherwise 55h. this ensures tha t 16 transitions are sent before the opening flag. bit [1] nb (smd.1) non - buffered mode. no control field contained in sdlc frame. bit [0] nfcs (smd.0) when set, selects no fcs field contained in the sdlc frame. ?
ia8044/ia8 344 data sheet sdlc communications controller march 30, 2010 ia211010112 - 0 4 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 38 of 65 1 - 888 - 824 - 4184 table 32 . seri al mode select clock mode bits scm 2 1 0 clock mode data rate (bits/sec) a 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 externally clocked undefined self clocked, timer overflow undefined self clocked, external 16x self clocked, external 32x self cl ocked, internal fixed self clocked, internal fixed 0 C 2.4m b 244 C 62.5k 0 C 375k 0 C 187.5k 375k 187.5k a based on a12 - mhz crystal frequency . b 0 C 1 m bps in loop configuration . 4.10.3 status/command register (sts) table 3 3 presents the status/command register, which pro vides siu control from and status to the cpu. the siu can read the sts and can write certain bits in the sts. the cpu can read and write the sts. accessing the sts by the cpu via two cycle instructions jbc bit,rel and mov bit,c should not be used. sts is bit addressable. table 33 . status/command register 7 6 5 4 3 2 1 0 tbf rbe rts si bov opb am rbp bit [7] tbf (sts.7) transmit buffer full. tbf is set by the cpu to indicate that the transmit buffer is ready and tbf is cleared by the siu. bit [6] rbe (sts.6) receive buffer empty. rbe is set by the cpu when it is ready to receive a frame or has just read the buffer. rbe is cleared by the siu when a frame has been received. can be thought of as a receive enable. bit [5] rts (sts.5) request to send. this bit is set when the siu is ready to transmit or is transmitting. may be written by the siu in auto mode . rts is only applied to the external pin in non - loop mode. can be thought of as a transmit enable. note: rts signal at the pin (p1.6) is the inverted version of this bit. bit [4] si (sts.4) siu interrupt. this bit is set by the siu and should be c leared by the cpu before returning from the interrupt routine. bit [3] bov (sts.3) receive buffer overrun. the siu can set or clear bov. ?
ia8044/ia8 344 data sheet sdlc communications controller march 30, 2010 ia211010112 - 0 4 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 39 of 65 1 - 888 - 824 - 4184 bit [2] opb (sts.2) optional poll bit. when set, the siu will auto respond to an optional poll (up with p=0). th e siu can set or clear the opb. bit [1] am (sts.1) auto mode. dual purpose bit depending upon the setting of bit nb (smd.1). if nb is cleared, am selects the auto mode when set, flexible mode when clear. if nb is set, am selects the addressed mode whe n set and the non - addressed mode when clear. the siu can clear am. bit [0] rbp (sts.0) receive buffer protect. when set, prevents writing of data into the receive buffer. causes rnr response instead of rr in auto mode. 4.10.4 send/receive count register (nsn r) table 3 4 presents the send/receive count register, which contains both the transmit and receive sequence numbers in addition to the tally error indications. the cpu can read and write the sts. accessing the sts by the cpu via two cycle instructions jb c bit,rel and mov bit,c should not be used. the siu can read and write the nsnr. the ns and nr counters are not used in non - auto mode. nsnr is bit addressable. table 34 . send/receive count register 7 6 5 4 3 2 1 0 ns2 ns1 ns0 s es nr2 nr1 nr0 ser bit [7] ns2 (nsnr.7) send sequence counter, bit [2]. bit [6] ns1 (nsnr.6) send sequence counter, bit [1]. bit [5] ns0 (nsnr.5) send sequence counter, bit [0]. bit [4] ses (nsnr.4) sequence error send. nr (p) ns (s) and nr (p ) ns (s) + 1. bit [3] nr2 (nsnr.3) receive sequence counter, bit [2]. bit [2] nr1 (nsnr.2) receive sequence counter, bit [1]. bit [1] nr0 (nsnr.1) receive sequence counter, bit [0]. bit [0] ser (nsnr.0) sequence error receive. ns (p) nr (s). ?
ia8044/ia8 344 data sheet sdlc communications controller march 30, 2010 ia211010112 - 0 4 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 40 of 65 1 - 888 - 824 - 4184 4.10.5 s tation address register (stad) table 3 5 presents the station address register, which contains the station address (node address) of the chip. the cpu can read or write stad but should access stad only when rts = 0 and rbe = 0. normally stad is accessed o nly during initialization. stad is byte addressable. table 35 . station address register 7 6 5 4 3 2 1 0 stad.7 stad.6 stad.5 stad.4 stad.3 stad.2 stad.1 stad.0 4.10.6 transmit buffer start address register (tbs) table 36 presents the transmit buffer start address register, which contains the address in internal ram where the frame to be transmitted (starting with the i - field) is stored. the cpu should access tbs only when the siu is not transmitting a frame, tbf = 0. tbs is byte add ressable. table 36 . transmit buffer start address register 7 6 5 4 3 2 1 0 tbs.7 tbs.6 tbs.5 tbs.4 tbs.3 tbs.2 tbs.1 tbs.0 4.10.7 transmit buffer length register (tbl) table 37 presents the transmit buffer length register, which contai ns the length, in number of bytes, of the i - field to be transmitted. tbl = 0 is valid (no i - field). the cpu should access tbl only when the siu is not transmitting a frame, tbf = 0. the transmit buffer will not wrap around after address 191 (bfh). a bu ffer end is automatically generated when address 191 is reached. tbl is byte addressable. table 37 . transmit buffer length register 7 6 5 4 3 2 1 0 tbl.7 tbl.6 tbl.5 tbl.4 tbl.3 tbl.2 tbl.1 tbl.0 4.10.8 transmit control byte register (tcb) table 38 presents the transmit control byte register, which contains the byte to be placed in the control field of the transmitted frame during non - auto - mode transmission. the cpu should access tcb only when the siu is not transmitting a frame, tbf = 0. tcb is byte addressable. ?
ia8044/ia8 344 data sheet sdlc communications controller march 30, 2010 ia211010112 - 0 4 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 41 of 65 1 - 888 - 824 - 4184 table 38 . transmit control byte register 7 6 5 4 3 2 1 0 tcb.7 tcb.6 tcb.5 tcb.4 tcb.3 tcb.2 tcb.1 tcb.0 4.10.9 receive buffer start address register (rbs) table 39 presents the receive buffer start addre ss register, which contains the address in internal ram where the frame (starting with the i - field) being received is to be stored. the cpu should write rbs only when the siu is not receiving a frame, rbe = 0. rbs is byte addressable. table 39 . receive buffer start address register 7 6 5 4 3 2 1 0 rbs.7 rbs.6 rbs.5 rbs.4 rbs.3 rbs.2 rbs.1 rbs.0 4.10.10 receive buffer length register (rbl) table 4 0 presents the receive buffer length register, which contains the length, in number of byte s, of the i - field storage area in internal ram. rbl = 0 is valid (no i - field). the cpu should write rbl only when the siu is not receiving a frame, rbe = 0. the receive buffer will not wrap around after address 191 (bfh). a buffer end is automatically generated when address 191 is reached. rbl is byte addressable. table 40 . receive buffer length register 7 6 5 4 3 2 1 0 rbl.7 rbl.6 rbl.5 rbl.4 rbl.3 rbl.2 rbl.1 rbl.0 4.10.11 receive field length register (rfl) table 4 1 presents the receive field length register, which contains the length, in number of bytes, of the i - field of the frame received and stored in internal ram. rfl = 0 is valid (no i - field). the cpu should access rfl only when the siu is not receiving a frame, rbe = 0. rfl is loaded by the siu. rfl is byte addressable. table 41 . receive field length register 7 6 5 4 3 2 1 0 rfl.7 rfl.6 rfl.5 rfl.4 rfl.3 rfl.2 rfl.1 rfl.0 4.10.12 receive control byte register (rcb) table 4 2 presents the receive contro l byte register, which contains the control field of the frame received and stored in internal ram. rcb is only readable by the cpu and the cpu should access rcb only when the siu is not receiving a frame, rbe = 0. rcb is loaded by the siu. rcb is byte addressable. ?
ia8044/ia8 344 data sheet sdlc communications controller march 30, 2010 ia211010112 - 0 4 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 42 of 65 1 - 888 - 824 - 4184 table 42 . receive control byte register 7 6 5 4 3 2 1 0 rcb.7 rcb.6 rcb.5 rcb.4 rcb.3 rcb.2 rcb.1 rcb.0 4.10.13 dma count register (dma cnt) table 4 3 presents the dma count register (dma cnt), which contains the number of b ytes remaining for the information field currently being used. this register is an ice support register. dma cnt is byte addressable. table 43 . dma count register (dma cnt) 7 6 5 4 3 2 1 0 dma cnt.7 dma cnt.6 dma cnt.5 dma cnt.4 dma cnt.3 d ma cnt.2 dma cnt.1 dma cnt.0 4.10.14 dma count register (fifo) table 4 4 presents the dma count register (fifo), which is actually three registers that make a three - byte fifo. these are used as temporary storage between the eight - bit shift register a nd the receive buffer when an information field is received. this register is an ice support register. fifo is byte addressable. table 44 . dma count register (fifo) 7 6 5 4 3 2 1 0 fifo# a .7 fifo# a .6 fifo# a .5 fifo# a .4 fifo# a .3 fi fo# a .2 fifo# a .1 fifo# a .0 a 1, 2, or 3 for fifo1, fifo2, or fifo3 , respectively. 4.10.15 siu state counter (siust) table 4 5 presents the siu state counter register, which indicates what state the siu state machine is currently in. this in turn indicates what task the siu is performing or which field is expected next by the siu. this register should not be written to. this register is an ice support register. siust is byte addressable. table 45 . siu state counter 7 6 5 4 3 2 1 0 siust .7 siust .6 siust .5 siust .4 siust .3 siust .2 siust .1 siust .0 ?
ia8044/ia8 344 data sheet sdlc communications controller march 30, 2010 ia211010112 - 0 4 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 43 of 65 1 - 888 - 824 - 4184 4.11 data clocking options the siu may be clocked in one of two ways, with an external clock or in a self - clocked mode. in the external clocked mode, a serial clock must be provided on sclk. th is clock must be synchronized to the serial data. incoming data is sampled at the rising edge of sclk. outgoing data is shifted out at the falling edge of sclk. in the self - clocked mode, the siu uses a reference clock and the serial data to reproduce t he serial data clock. the reference clock can be an external source applied to sclk, the ia8044/ia8344s internal clock or the timer 1 overflow. the reference clock must be 16 or 32 the data rate. a dpll uses the reference clock and the serial data to adjust the sample time to the center of the serial bit. it does this by adjusting from a serial data transition in increments of 1/16 of a bit time. the maximum data rate in the externally clocked mode is 2.4 mbps in a point - to - point configuration and 1.0 mbps in a loop configuration. with a 12 - mhz cpu clock, the maximum data rate in the self - clocked mode with an external clock is 375 kbps. the maximum data rate in the self - clocked mode with an internal clock will depend on the frequency of the ia8044 /ia8344s input clock. an ia8044/ia8344 using a 12 - mhz input clock can operate at a maximum data rate of 375 kbps. the serial mode register bits [5], [6], and [7] select the clocking option for the siu (see smd register description). 4.12 operational modes the siu operates in one of two modes, auto or flexible. the mode selected determines how much intervention is required by the cpu when receiving and transmitting frames. in both modes, short frames, aborted frames, and frames with crc errors will be ignored . auto mode allows the siu to recognize and respond to specific sdlc frames without the cpus intervention. this provides for a faster turnaround time but restricts the operation of the siu. when in auto mode, the siu can only act as a normal response se condary station and responses will adhere to ibms sdlc definitions. when receiving in the auto mode, the siu receives the frame and examines the control byte. it will then take the appropriate action for that frame. if the frame is an information frame, the siu will load the receive buffer, interrupt the cpu and make the required response to the primary station. the siu in auto mode can also respond to the following commands from the primary station: rr (receive ready) rnr (receive not ready) rej (rejec t) ?
ia8044/ia8 344 data sheet sdlc communications controller march 30, 2010 ia211010112 - 0 4 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 44 of 65 1 - 888 - 824 - 4184 up (unnumbered poll) also called nsp, (non - sequenced poll), or orp (optional response poll) in auto mode when the transmit buffer is full, the siu can transmit an information frame when polled for information. after transmission the siu waits for ackno wledgement from the receiving station. if the response is positive, the siu interrupts the cpu. if the response is negative, the siu retransmits the frame. the siu can send the following responses to the primary station: rr (receive ready) rnr (receive not ready) the flexible mode requires the cpu to control the siu for both transmitting and receiving. this slows response time but allows full sdlc and limited hdlc compatibility as well as variations. in flexible mode, the siu can act as a primary stati on. the siu will interrupt the cpu after completion of a transmission without waiting for a positive acknowledgement from the receiving station (see table 46 ). table 46 . basic sdlc frame flag address control information fcs flag ia8044/ia8344 frame parameters: flag 8 bits address 8 bits control 8 bits information n bytes (where n 192) fcs 16 bits flag 8 bits 4.13 frame format options the various frame formats available with the ia8044/ia8344 are the standard sdlc format, the no - cont rol field format, the no - control field and no - address field formats, and the no - fcs field format. the standard sdlc format consists of an opening flag, an 8 - bit address field, an 8 - bit control field, an n - byte information field, a 16 - bit frame check sequ ence field, and a closing flag. the fcs is generated by the ccit - crc polynomial (x16 + x12 + x5 + 1). the fcs is calculated on the address, control, and information fields. the address and control fields may not be extended. the address is contained in stad and the control filed is contained in either rcb or tcb. this format is supported by both auto and flexible modes. ?
ia8044/ia8 344 data sheet sdlc communications controller march 30, 2010 ia211010112 - 0 4 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 45 of 65 1 - 888 - 824 - 4184 the no - control field format is only supported by the flexible mode. in this format, tcb and rcb are not used and the information fiel d starts immediately after the address field. a control field may still be used in the frame but the siu will treat it as a byte of the information field. the no - control field and no - address field formats are supported only by the flexible mode. in this format stad, tcb, and rcb are not used and the information field starts immediately after the opening flag. this option can only be used with the no - control field option. a control field and address field may still be used in the frame but the siu will t reat each as a byte of the information field. the no fcs field format prevents an fcs from being generated during transmission or being checked during reception. this option may be used in conjunction with the other frame format options. this option will work with both flexible and auto modes. in auto mode, it could cause protocol violations. an fcs field may still be used in the frame but the siu will treat it as a byte of the information field. all the possible frame format combinations are presented in table 47 , along with the bit settings that select a given format. table 47 . frame format options frame option nfcs nb am frame format standard sdlc flexible mode 0 0 0 fl ad co inf fcs fl standard sdlc auto mode 0 0 1 fl ad co inf fcs fl no - control field flexible mode 0 1 1 fl ad inf fcs fl no - control field no - address field flexible mode 0 1 0 fl inf fcs fl no - fcs field flexible mode 1 0 0 fl ad co inf fl no - fcs field auto mode 1 0 1 fl ad co inf fl ?
ia8044/ia8 344 data sheet sdlc communications controller march 30, 2010 ia211010112 - 0 4 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 46 of 65 1 - 888 - 824 - 4184 frame option nfcs nb am frame format no - control field no - fcs field flexible mode 1 1 1 fl ad inf fl no - control field no - address field no - fcs field flexible mode 1 1 0 fl inf fl ad = address field co = control field fcs = frame check sequence fl = flag inf = information field 4.14 hdlc restrictions the ia8044/ia8344 supports a subset of the hdlc protocol. the differences include the restriction by the ia8044/ia8344 of the serial data to be in 8 - bit increments. in contrast, hdlc allows for any number of bits in the information field. hdlc provides an unlimited address field and an extended frame number sequencing. hdlc does not support loop configuration. 4.15 siu details the siu is composed of two functional blocks with each having several sub blocks. the two blocks are called the bit processor (bip) and the byte processor (byp) (see figure 11). 4.15.1 bip the bip consists of the dpll, nrzi encoder/decoder, serial/parallel shifter, zero insertion/deletion, shutoff logic, and fcs generation/checking. the nrzi logic compares the current bit to the previous bit to determine if the bit should be inverted. the serial shifter converts the outgoing byte data to bit data and incoming bit data to byte data. the zero insert/delete circuitry inserts and deletes zeros and also detects flags (01111110), go - aheads (ga) ( 01111111), and aborts (1111111). the pattern 1111110 is detected as an early go - ahead that can be turned into a flag in loop configurations. the shutoff detector is a three - bit counter that is used to detect a sequence of eight zeros, which is the shutof f command in loop - mode transmissions. it is cleared whenever a D1 is detected. the fcs logic performs the generation and checking of the fcs value according to the polynomial described above. the fcs register is set to all 1s prior to each calculation. if a crc error is generated on a receive frame, the siu will not interrupt the cpu and the error will be cleared upon receiving an opening flag. ?
ia8044/ia8344 data sheet sdlc communications controller march 30, 2010 ia211010112 - 0 4 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 47 of 65 1 - 888 - 824 - 4184 figure 11 . bit and byte processors ? d i v b y 2 d p l l b i t t i m i n g g e n e r a t o r n r z i e n c o d e / d e c o d e z e r o i n s e r t / d e l e t e s e r i a l / p a r a l l e l s h i f t e r s t a r t d e t e c t f c s g e n e r a t o r / c h e c k e r c o n t r o l s t a t e m a c h i n e d e c i s i o n l o g i c i n t e r n a l r a m s i u s f r s i n t c l k t 1 o v r f l w s c l k r x d t x d b i t p r o c e s s o r b y t e p r o c e s s o r s e r i a l i n f o r m a t i o n b u s i n f o r m a t i o n b u s
ia8044/ia8344 data sheet sdlc communications controller march 30, 2010 ia211010112 - 0 4 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 48 of 65 1 - 888 - 824 - 4184 4.15.2 byp the byp contains registers and controlle rs used to perform the manipulations required for sdlc communications. the byp registers may be accessed by the cpu (see table 7 , sfr bit addressable locations ). the byp contains the siu state machine that controls transmission and reception of frames. 4.16 diagnostics a diagnostic mode is included with the ia8044/ia8344 to allow testing of the siu. diagnostics use port pins p3.0 and p3.1. writing a D0 to p3.1 enables the diagnostic mode. when p3.1 is cleared , writing data to p3.0 has the effect of writing a serial data stream to the siu. p3.0 is the serial data and any write to port 3 will clock sclk. the transmit data may be monitored on p3.1 with any write to port 3, again clocking sclk. in the test mode p3.0 and p3.1 pins are placed in the high impedance state (see figure 12). ?
ia8044/ia8344 data sheet sdlc communications controller march 30, 2010 ia211010112 - 0 4 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 49 of 65 1 - 888 - 824 - 4184 figure 12 . diagnostic signal routing ? s c l k p i n r x d p i n t x d p i n q d q d q d t 1 o v r f s y s c l k p 3 . 5 o u t l a t c h p 3 . 0 o u t l a t c h l o o p w r i t e p o r t 3 s i u t x d a t a o u t p i n 3 . 1 o u t l a t c h s i u r x d a t a i n s i u s e r i a l d a t a c l k
ia8044/ia8344 data sheet sdlc communications controller march 30, 2010 ia211010112 - 0 4 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 50 of 65 1 - 888 - 824 - 4184 5. ac specifications ac characteristics, external data memory characteristics, serial interface characteristics, and external clock drive characteristics are provided in tables 48 through 51 , respectively. t a = ? 40 c to +85 c, vdd = 5v 10%, vss = 0v, load capacitance = 87pf table 48 . external program memory characteristics symbol parameter 12 mhz osc variable clock 1/tclcl = 3.5 mhz to 12 mhz unit min max min max tlhll ale p ulse width 171 C 2tclcl+4 C ns tavll address valid to ale low 75 C tclcl - 8 C ns tllax address hold after ale low 74 C tclcl - 9 C ns tlliv ale low to valid instr. in. C 298 C 4tclcl - 35 ns tllpl ale low to psenn low 83 C tclcl C ns tplph psenn pulse widt h 254 C 3tclcl+4 C ns tpliv psenn low to valid instr. in C 215 C 3tclcl - 35 ns tpxix input instr. hold after psenn 0 C 0 C ns tpxiz input instr. float after psenn C 76 C tclcl - 7 ns tpxav psenn to address valid 91 C tclcl+8 C ns taviv address to valid i nstr. in C 373 C 5tclcl - 43 ns tazpl address float to psenn - 9 C - 9 C ns tcy machine cycle 996 C 12tclcl C ns table 49 . external data memory characteristics symbol parameter 12 mhz osc variable clock 1/tclcl = 3.5 mhz to 12 mhz unit min max min max trlrh rdn pulse width 487 C 6tclcl - 13 C ns twlwh wrn pulse width 487 C 6tclcl - 13 C ns tllax address hold after ale 74 C tclcl - 9 C ns trldv rdn low to valid data in C 383 C 5tclcl - 35 ns trhdx data hold after rdn 0 C 0 C n s trhdz data float after rdn C 165 C 2tclcl - 2 ns tlldv ale low to valid data in C 633 C 8tclcl - 34 ns tavdv address to valid data in C 708 C 9tclcl - 42 ns tllwl ale low to rdn or wrn low 250 250 3tclcl 3tclcl ns tavwl address to rdn or wrn low 325 C 4t clcl - 8 C ns tqvwx data valid to wrn transi tion 76 C tclcl - 7 C ns tqvwh data setup before wrn high 563 C 7tclcl - 20 C ns twhqx data held after wrn 86 C tclcl+3 C ns ?
ia8044/ia8344 data sheet sdlc communications controller march 30, 2010 ia211010112 - 0 4 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 51 of 65 1 - 888 - 824 - 4184 trlaz rdn low to address float C C table 50 . serial interface characteristics symbol parameter min max unit tdcy data clock 420 C ns tdcl data clock low 184 C ns tdch data clock high 184 C ns ttd transmit data delay C 125 ns tdss data setup time 26 C ns tdhs data hold time 58 C ns table 51 . external clock drive characteristics symbol parameter min max unit tclcl oscillator period 52 C ns 5.1 memory access waveforms the ia8044/ia8344 program memory read cycle, data memory rea d cycle, and data memory write cycle are presented in figures 13 through 15, respectively. ?
ia8044/ia8344 data sheet sdlc communications controller march 30, 2010 ia211010112 - 0 4 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 52 of 65 1 - 888 - 824 - 4184 figure 13 . program memory read cycle ? ale psenn port_0 port_2 instr. in a7 - a0 instr. in a7 - a0 instr. in i nstr. in address or sfr - p2 address a15 - a8 address a15 - a8 address a15 - a8 tcy tlhll tlliv tllpl tplph tavll tpliv tazpl taviv tllax tpxav tpxiz tpxix
ia8044/ia8344 data sheet sdlc communications controller march 30, 2010 ia211010112 - 0 4 http://www.innovasic.com uncontrolled when pr inted or copied customer su pport: page 53 of 65 1 - 888 - 824 - 4184 figure 14 . data me mory read cycle ? ale psenn rdn port_0 port_2 a7 - a0 data in address a15 - a8 or sfr - p2 address a15 - a8 or sfr - p2 twhlh trlrh tllwl tavwl tlldv tllax trldv trlaz trhdz trhdx tavdv
ia8044/ia8344 data sheet sdlc communications controller march 30, 2010 ia211010112 - 0 4 http://www.innovasic.com uncontrolled when pr inted or copied customer su pport: page 54 of 65 1 - 888 - 824 - 4184 figure 15 . data memory write cycle ? ale psenn wrn port_0 port_2 a7 - a0 data out data out address a15 - a8 or sfr - p2 address a15 - a8 or sfr - p2 tavwl tllax twlwh twhlh twhqx tllw l tqvwx tqvwh
ia8044/ia8344 data sheet sdlc communications controller march 30, 2010 ia211010112 - 0 4 http://www.innovasic.com uncontrolled when pr inted or copied customer su pport: page 55 of 65 1 - 888 - 824 - 4184 5.2 serial i/o waveforms the ia8044/ia8344 synchronous data transmission and synchronous data reception are presented in figures 16 and 17, respectively. figure 16 . synchronous data transmission figure 17 . synchronous data reception ? sclk data tdcl ttd tdch tdcy sclk data tdhs tdss tdch tdcl tdcy
ia8044/ia8344 data sheet sdlc communications controller march 30, 2010 ia211010112 - 0 4 http://www.innovasic.com uncontrolled when pr inted or copied customer su pport: page 56 of 65 1 - 888 - 824 - 4184 6. reset a reset is accomplished by holding the rst pin high for at l east two machine cycles (24 oscillator periods) while the oscillator is running. the cpu responds by generating an internal reset, which is executed during the second cycle in which rst is high. the internal reset sequence affects all sfrs as shown in tab le 52 . the internal reset sequence does not affect the contents of internal ram. table 52 . reset values register register reset value pc 0000h acc 00000000b b 00000000b psw 00000000b sp 00000111b dptr 0000h p0 C p3 111 11111b ip xxx00000b ie 0xx00000b tmod 00000000b tcon 00000000b th0 00000000b tl0 00000000b th1 00000000b tl1 00000000b smd 00000000b sts 00000000b nsnr 00000000b stad xxxxxxxxb tbs xxxxxxxxb tbl xxxxxxxxb tcb xxxxxxxxb rbs xxxxxxx xb rbl xxxxxxxxb rfl xxxxxxxxb rcb xxxxxxxxb dma cnt 00000000b fifo1 00000000b fifo2 00000000b fifo3 00000000b siust 00000001b ?
ia8044/ia8344 data sheet sdlc communications controller march 30, 2010 ia211010112 - 0 4 http://www.innovasic.com uncontrolled when pr inted or copied customer su pport: page 57 of 65 1 - 888 - 824 - 4184 7. instruction set the ia8044 and ia8344 architecture and instruction set are identical to the intel 8051s. tables 53 th rough 57 present the instruction set of the ia8044/ia8344 microcontroller core. table 53 . arithmetic operations mnemonic description byte cycle add a,rn add register to accumulator 1 1 add a, direct add direct byte to accumulat or 2 1 add a,@ri add indirect ram to accumulator 1 1 add a,#data add immediate data to accumulator 2 1 addc a,rn add register to accumulator with carry flag 1 1 addc a,direct add direct byte to a with carry flag 2 1 addc a,@ri add indirect r am to a with carry flag 1 1 addc a,#data add immediate data to a with carry flag 2 1 subb a,rn subtract register from a with borrow 1 1 subb a,direct subtract direct byte from a with borrow 2 1 subb a,@ri subtract indirect ram from a with borro w 1 1 subb a,#data subtract immediate data from a with borrow 2 1 inc a increment accumulator 1 1 inc rn increment register 1 1 inc direct increment direct byte 2 1 inc @ ri increment indirect ram 1 1 dec a decrement accumulator 1 1 dec r n decrement register 1 1 dec direct decrement direct byte 2 1 dec @ri decrement indirect ram 1 1 inc dptr increment data pointer 1 2 mul a,b multiply a and b 1 4 div a,b divide a by b 1 4 da a decimal adjust accumulator 1 1 ?
ia8044/ia8344 data sheet sdlc communications controller march 30, 2010 ia211010112 - 0 4 http://www.innovasic.com uncontrolled when pr inted or copied customer su pport: page 58 of 65 1 - 888 - 824 - 4184 table 54 . logic operations mnemonic description byte cycle anl a,rn and register to accumulator 1 1 anl a,direct and direct byte to accumulator 2 1 anl a,@ri and indirect ram to accumulator 1 1 anl a,#data and immediate data to acc umulator 2 1 anl direct,a and accumulator to direct byte 2 1 anl direct,#data and immediate data to direct byte 3 2 orl a,rn or register to accumulator 1 1 orl a,direct or direct byte to accumulator 2 1 orl a,@ri or indirect ram to accumulator 1 1 orl a,#data or immediate data to accumulator 2 1 orl direct,a or accumulator to direct byte 2 1 orl direct,#data or immediate data to direct byte 3 2 xrl a,rn exclusive or register to accumulator 1 1 xrl a,direct exclusive or direct byte t o accumulator 2 1 xrl a,@ri exclusive or indirect ram to accumulator 1 1 xrl a,#data exclusive or immediate data to accumulator 2 1 xrl direct,a exclusive or accumulator to direct byte 2 1 xrl direct,#data exclusive or immediate data to direct b yte 3 2 clr a clear accumulator 1 1 cpl a complement accumulator 1 1 rl a rotate accumulator left 1 1 rlc a rotate accumulator left through carry 1 1 rr a rotate accumulator right 1 1 rrc a rotate accumulator right through carry 1 1 swap a swap nibbles within the accumulator 1 1 ?
ia8044/ia8344 data sheet sdlc communications controller march 30, 2010 ia211010112 - 0 4 http://www.innovasic.com uncontrolled when pr inted or copied customer su pport: page 59 of 65 1 - 888 - 824 - 4184 table 55 . data transfer mnemonic description byte cycle mov a,rn move register to accumulator 1 1 mov a,direct move direct byte to accumulator 2 1 mov a,@ri move indirect ram to accumulator 1 1 mov a,#data move immediate data to accumulator 2 1 mov rn,a move accumulator to register 1 1 mov rn,direct move direct byte to register 2 2 mov rn,#data move immediate data to register 2 1 mov direct,a move accumulator to d irect byte 2 1 mov direct,rn move register to direct byte 2 2 mov direct,direct move direct byte to direct byte 3 2 mov direct,@ri move indirect ram to direct byte 2 2 mov direct,#data move immediate data to direct byte 3 2 mov @ri,a move acc umulator to indirect ram 1 1 mov @ri,direct move direct byte to indirect ram 2 2 mov @ ri, #data move immediate data to indirect ram 2 1 mov dptr, #data16 load data pointer with a 16 - bit constant 3 2 movc a,@a + dptr move code byte relative to dptr to accumulator 1 2 movc a,@a + pc move code byte relative to pc to accumulator 1 2 movx a,@ri move external ram (8 - bit address ) to a 1 2 movx a,@dptr move external ram (16 - bit address ) to a 1 2 movx @ri,a move a to external ram (8 - bit addres s ) 1 2 movx @dptr,a move a to external ram (16 - bit address ) 1 2 push direct push direct byte onto stack 2 2 pop direct pop direct byte from stack 2 2 xch a,rn exchange register with accumulator 1 1 xch a,direct exchange direct byte with accumu lator 2 1 xch a,@ri exchange indirect ram with accumulator 1 1 xchd x,@ ri exchange low - order nibble indirect ram with a 1 1 ?
ia8044/ia8344 data sheet sdlc communications controller march 30, 2010 ia211010112 - 0 4 http://www.innovasic.com uncontrolled when pr inted or copied customer su pport: page 60 of 65 1 - 888 - 824 - 4184 table 56 . boolean manipulation mnemonic description byte cycle clr c clear carry flag 1 1 clr b it clear direct bit 2 1 setb c set carry flag 1 1 setb bit set direct bit 2 1 cpl c complement carry flag 1 1 cpl bit complement direct bit 2 1 anl c,bit and direct bit to carry flag 2 2 anl c,bit and complement of direct bit to carry 2 2 orl c,bit or direct bit to carry flag 2 2 orl c,bit or complement of direct bit to carry 2 2 mov c,bit move direct bit to carry flag 2 1 mov bit,c move carry flag to direct bit 2 2 table 57 . program branches mnemonic description byte cycle acall addr11 absolute subroutine call 2 2 lcall addr16 long subroutine call 3 2 ret return from subroutine 1 2 reti return from interrupt 1 2 ajmp addr11 absolute jump 2 2 ljmp addr16 long jump 3 2 sjmp rel short jum p (relative addr ess ) 2 2 jmp @a + dptr jump indirect relative to the dptr 1 2 jz rel jump if accumulator is zero 2 2 jnz rel jump if accumulator is not zero 2 2 jc rel jump if carry flag is set 2 2 jnc rel jump if carry flag is not set 2 2 j b bit,rel jump if direct bit is set 3 2 jnb bit,rel jump if direct bit is not set 3 2 jbc bit,rel jump if direct bit is set and clear bit 3 2 cjne a,direct,rel compare direct byte to a and jump if not equal 3 2 cjne a,#data,rel compare immediate to a and jump if not equal 3 2 cjne rn,#data rel compare immediate to register and jump if not equal 3 2 cjne @ri,#data,rel compare immediate to indirect and jump if not equal 3 2 djnz rn,rel decrement register and jump if not zero 2 2 djnz dir ect,rel decrement direct byte and jump if not zero 3 2 nop no operation 1 1 ?
ia8044/ia8344 data sheet sdlc communications controller march 30, 2010 ia211010112 - 0 4 http://www.innovasic.com uncontrolled when pr inted or copied customer su pport: page 61 of 65 1 - 888 - 824 - 4184 8. innovasic/intel part number cross - referenc e tables table s 5 8 and 59 cross - reference each innovasic part number with the corresponding intel part number for the pdip and plcc , respectively . table 58 . innovasic /intel part number cross - reference for the pdip innovasic part number intel part number package type temperature grades ia8x 44 pdw40ir3 lead - free ( rohs ) P8344 P8344ah tP8344ah p8044 p8044ah p8044a h - r0117 tp8044ah tp8044ah - r0117 40 - pin p lastic d ual i n - line p ackage (pdip) (600 mils) industrial ia8x 44 pdw40i3 lead frame ( snpb ) table 59 . innovasic /intel part number cross - reference for the plc c innovasic part number intel p art number package type temperature grades ia8x 44 - plc44i - r - p0 3 lead - free ( rohs ) n8344 n8344ah tn8344ah n8044 n8044ah n8044ah - r0117 tn8044ah tn8044ah - r0117 8044ahn 8044an 44 - pin p lastic l eaded c hip c arrier (plcc) industrial ia8x 44plc44i3 lead frame ( snpb) ?
ia8044/ia8344 data sheet sdlc communications controller march 30, 2010 ia211010112 - 0 4 http://www.innovasic.com uncontrolled when pr inted or copied customer su pport: page 62 of 65 1 - 888 - 824 - 4184 9. errata 9.1 summary table 60 presents a summary of errata in the ia8044/ia8344 controller . table 60 . summary of errata errata no. problem ver. 3 1 cannot read internal rom with eprom verification method . exists 2 the device has a different pullup value than the intel version. exists 3 the device responds to an idle flag one bit time too early. exists 4 under certain condit ions the siu will overwrite the rcb register when starting a transmission. exists 9.2 detail errata no. 1 problem: cannot read internal rom with eprom verification method. description: the ia8044/ia8344 does not contain internal ep rom and therefore does not support the eprom read feature. workaround: must use alternate method to read internal rom. errata no. 2 problem: the device has a different pullup value than the intel version. description: the i ntel version can source more current than the ia8044/ia8344. workaround: adjust external circuits if necessary. ?
ia8044/ia8344 data sheet sdlc communications controller march 30, 2010 ia211010112 - 0 4 http://www.innovasic.com uncontrolled when pr inted or copied customer su pport: page 63 of 65 1 - 888 - 824 - 4184 errata no. 3 problem: the device responds to an i dle flag one bit time too early. description: this causes problems in a loop - mode network. it only occurs in loop mode when using an external siu clock source and idle flags. workaround: none. errata no. 4 problem: under certain conditions the siu will overwrite the rcb register when starting a transmission. description: the conditions are: the siu is externally clocked . the siu is in flexible mode . the cpu has not already read the rcb from a previous reception before the transmission takes place. workaround: read the rcb before initiating a transmit. ?
ia8044/ia8344 data sheet sdlc communications controller march 30, 2010 ia211010112 - 0 4 http://www.innovasic.com uncontrolled when pr inted or copied customer su pport: page 64 of 65 1 - 888 - 824 - 4184 10. revision history table 61 presents the sequence of revisions to document ia 2110 10112 . table 61 . revision history date revision description page(s) january 20, 2006 01 first edition released . na august 28, 2007 02 upda ted rohs info, header, footer, cover page. errata added. all january 2, 2009 0 3 reformatted and reorganized to meet publication standards. technical data updated. Dsummary of errata table added. all march 30, 2010 04 updated innovasic part numbers on cross reference table to reflect current part marking scheme. (part is still version 3 release.) 61 ?
ia8044/ia8344 data sheet sdlc communications controller march 30, 2010 ia211010112 - 0 4 http://www.innovasic.com uncontrolled when pr inted or copied customer su pport: page 65 of 65 1 - 888 - 824 - 4184 11. for additional information the innovasic semiconductor ia8044 and ia8344 are D plug - and - play drop - in replacements and are form, fit, and function compati ble parts to the intel 8044 and 8344. the ia8044 and ia8344 replace the obsolete intel 8044 and 8344, allowing users to retain existing board designs, software compilers/assemblers, and emulation tools thus avoiding expensive redesign efforts. the innova sic support team is continually planning and creating tools for your use. visit http://www.innovasic.com for up - to - date documentation and software. our goal is to provide timely, complete, accurate, useful, and e asy - to - understand information . please feel free to contact our experts at innovasic at any time with suggestions, comments, or questions. innovasic support team 3737 princeton ne suite 130 albuquerque, nm 87107 (505) 883 - 5263 fax: (505) 883 - 5477 toll f ree: (888) 824 - 4184 e - mail: support@innovasic.com website: http://www.innovasic.com ?

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